Deferred setting of scheduling attributes in Ada 2012

© Sáez Barona, S.; Crespo, A. | ACM, 2015. This is the author's version of the work. It is posted here for your personal use. Not for redistribution. The definitive Version of Record was published in Adda Letters, http://dx.doi.org/10.1145/2492312.2492322[EN] Some scheduling techniques, specially in multiprocessor systems, require changing several task attributes atomically to avoid scheduling errors and artifacts. This work proposes to incorporate the deferred attribute setting mechanism to cope with this problem in the next Ada 2012.This work was partially supported by the Vicerectorado de Investigacion of the Universidad Polit ´ ecnica de Valencia under grant PAID-06-10-2397 and European Project OVERSEE (ICT-2009 248333)Sáez Barona, S.; Crespo, A. (2013). Deferred setting of scheduling attributes in Ada 2012. Ada Letters. 33(1):93-100. https://doi.org/10.1145/2492312.2492322S9310033

A Hardware Architecture for Scheduling Complex Real-Time Task Sets

The problem of jointly scheduling both hard deadline periodic tasks and soft aperiodic tasks has been the subject of considerable research in real-time systems. One of the most widely accepted solutions for this problem are slack stealing algorithms. However, these algorithms are rather impractical, since they all imply a considerable scheduler overhead. This paper faces the overhead problem by introducing a complete hardware architecture that implements slack stealing in hardware using an optimal algorithm redesigned to be implemented efficiently in hardware. The proposed solution is a circuit that behaves as a kind of sophisticated interrupt controller taking the task workload and the interrupts as inputs, and providing the highest priority task to be executed in the CPU. From the point of view of hardware design, the algorithm involves two main problems: first, to select the highest priority task at every moment and, second, to locate a set of slack gaps in a real-time computation. Locating slack gaps in a real-time computation is a problem that requires to “look forward in time” into the forecast schedule of a given workload. This paper analyses the different approaches for solving this problem and presents a novel architecture to solve it efficiently using a technique based on an event-driven simulation of the future of a real-time computation. A timing analysis of the proposed design is also presented

Deferred and atomic setting of scheduling attributes for ada

© Sáez Barona, S.; Real Sáez, J.; Crespo, A. | ACM, 2015. This is the author's version of the work. It is posted here for your personal use. Not for redistribution. The definitive Version of Record was published in Adda Letters, http://dx.doi.org/10.1145/2552999.2553010Deferred setting of scheduling attributes refers to a single operation that sets a new value for a scheduling attribute of a task at some future time. Although deferred setting of scheduling attributes is possible in Ada 2012, it is in a rather limited way: only deadline or CPU can be changed deferredly, either at a specified time or when the task is released from a suspension object. And only one of those two attributes at a time. Other scheduling attributes such as priority cannot have deferred setting by means of a single operation. This would be a convenient feature to have for schemes such as job partitioning, task splitting, or mode changes. Another issue is the absence of operations for atomically changing several parameters at a time, which would avoid scheduling issues specially on multiprocessors. In this paper we explore a proposal aimed at correcting these two drawbacks. On one hand, we want to be able to change more attributes, not only deadlines, deferredly or immediately. On the other hand, we want to atomically change (now or later) a set of attributes, thereby avoiding scheduling artifacts that arise from sequentially changing several attributes, specially when the CPU is one of them. Rather than providing a number of library operations for postponing the setting of a variety of scheduling attributes, we propose to encapsulate the scheduling attributes of each task i n a single t agged type that can be extended with more attributes for specific applications if neededSáez Barona, S.; Real Sáez, JV.; Crespo, A. (2013). Deferred and atomic setting of scheduling attributes for ada. Ada Letters. 33(2):97-108. doi:10.1145/2552999.2553010S9710833

A hierarchical architecture for time- and event-triggered real-time systems

[EN] This paper proposes an architecture for combining the execution of time- and event-triggered real-time task sets. This makes it possible for the designer to choose the most appropriate mechanism depending on the role and nature of each task in the system. The proposed architecture allows one to choose the priority levels at which time- and event-triggered tasks are executed. This gives the designer an additional degree of freedom to make compromise decisions upon contradicting timing requirements, such as granting reduced jitter and at the same time providing prompt service to non-periodic events, for example. The proposed model is accompanied with a Ravenscar implementation of the time-triggered scheduler and a library of utilities for specifying time-triggered schedules and reusing time-triggered task patterns.This work has been partly supported by Spanish Government and FEDER funds (AEI/FEDER, UE) under grant (TIN2017-86520-C3-1-R) (PRECON-I4); and by European Commission project AQUAS (ECSEL-JU, Contract 737475).Real Sáez, JV.; Sáez Barona, S.; Crespo, A. (2019). A hierarchical architecture for time- and event-triggered real-time systems. Journal of Systems Architecture. 101:1-15. https://doi.org/10.1016/j.sysarc.2019.101652S11510

Ravenscar Support for Time-Triggered Scheduling

[EN] This position paper follows from a previous proposal to integrate a time-triggered scheduler in a prioritybased, preemptive scheduler such as that supported by Ada¿s task dispatching policy FIFO Within Priorities . The resulting combined scheduling carries the advantages of both time-triggered and priority-based scheduling, and helps mitigating their drawbacks. The paper presents a system model for the time-triggered subsystem that extends the original proposal, and describes a Ravenscar implementation of the scheduler at the run-time system level, in the form of a new package Ada.Dispatching.TTS. Multiple programming patterns can be implemented on top of this scheduler. With respect to the previously proposed full-Ada implementation, only patterns that implied the use of asynchronous transfer of control have been excluded. On the other hand, the extension of the original model enables new patterns, not supported in our previous proposal, using the new types of continuation and optional slots. We hold that bringing the time-triggered paradigm to Ravenscar is both feasible and convenient for the High-Integrity and Embedded application domains.This work has been partly supported by the Spanish Government’s project M2C2 (TIN2014-56158-C4-1-P-AR) and the European Commission’s projects ENABLE-S3 and AQUAS (ECSEL-JU, Contracts 692455 and 737475)Real Sáez, JV.; Sáez Barona, S.; Crespo, A. (2018). Ravenscar Support for Time-Triggered Scheduling. ACM SIGAda Ada Letters. 38(1):41-54. https://doi.org/10.1145/3241950.3241957S4154381M. Aldea and M. González-Harbour. MaRTE OS: An Ada Kernel for Real-Time Embedded Applications. Reliable Software Technologies - Ada Europe 2001, Lecture Notes in Computer Science, 2043:305-316, 2001.ISO/IEC-JTC1-SC22-WG9. Ada Reference Manual ISO/IEC 8652:2012(E). URL: http://www.ada-europe.org/manuals/LRM-2012.pdf, 2012.J. Leung and J. Whitehead. On the complexity of xed-priority scheduling of periodic, real-time tasks. Performance Evaluation (Netherlands), 2(4):237-250, 1982.C. Liu and J. Layland. Scheduling Algorithms for Multiprogramming in a Hard Real-Time Environment. Journal of the ACM, 20(1):46-61, 1973.J. Real and P. Rogers. Session Summary: Experience. Ada Letters, 36(1):101-102, June 2016.J. Real, S. Sáez, and A. Crespo. Combined scheduling of time-triggeed plans and priority scheduled task sets. Ada Letters, 36(1):68-76, June 2016.J. Real, S. Sáez, and A. Crespo. Combining time-triggered plans with priority scheduled task sets. In M. Bertogna and L. M. Pinho, editors, Reliable Software Technologies - Ada-Europe 2016, volume 9695 of Lecture Notes in Computer Science. Springer, June 2016.S. Sáez and J. Real. TTS Ravenscar runtime. https://doi.org/10.5281/zenodo.1168723, February 2018

MultiPARTES: Multicore Virtualization for Mixed-Criticality Systems

Modern embedded applications typically integrate a multitude of functionalities with potentially different criticality levels into a single system. Without appropriate preconditions, the integration of mixed-criticality subsystems can lead to a significant and potentially unacceptable increase of engineering and certification costs. A promising solution is to incorporate mechanisms that establish multiple partitions with strict temporal and spatial separation between the individual partitions. In this approach, subsystems with different levels of criticality can be placed in different partitions and can be verified and validated in isolation. The MultiPARTES FP7 project aims at supporting mixed- criticality integration for embedded systems based on virtualization techniques for heterogeneous multicore processors. A major outcome of the project is the MultiPARTES XtratuM, an open source hypervisor designed as a generic virtualization layer for heterogeneous multicore. MultiPARTES evaluates the developed technology through selected use cases from the offshore wind power, space, visual surveillance, and automotive domains. The impact of MultiPARTES on the targeted domains will be also discussed. In a number of ongoing research initiatives (e.g., RECOMP, ARAMIS, MultiPARTES, CERTAINTY) mixed-criticality integration is considered in multicore processors. Key challenges are the combination of software virtualization and hardware segregation and the extension of partitioning mechanisms to jointly address significant non-functional requirements (e.g., time, energy and power budgets, adaptivity, reliability, safety, security, volume, weight, etc.) along with development and certification methodology

Procedimiento de diseño para minimizar el consumo de potencia y los retrasos en WSAN

ResumenActualmente existe un gran interés por el desarrollo de aplicaciones industriales utilizando redes inalámbricas, principalmente por el aumento de la flexibilidad del sistema y la disminución de los costos de implementación. Sin embargo, los retrasos y el jitter que introduce la red de comunicaciones en las aplicaciones de control, han dado lugar a que en algunos casos no se obtenga una buena correspondencia entre los resultados experimentales y los objetivos de control propuestos, esto como consecuencia del uso de modelos imprecisos para analizar y diseñar estos sistemas, métodos de validación poco elaborados y plataformas que no soportan los modelos empleados. En este trabajo se presenta un procedimiento de diseño que permite encontrar un modo de funcionamiento óptimo del sistema, que garantiza el cumplimiento de los plazos de tiempo de las aplicaciones, y minimiza el consumo de potencia y los retrasos

Implementation of Timing-Event Affinities in Ada/Linux

© Sáez Barona, S.; Real Sáez, J. V.; Crespo, A. | ACM, 2015. This is the author's version of the work. It is posted here for your personal use. Not for redistribution. The definitive Version of Record was published in Adda Letters, http://dx.doi.org/10.1145/2870544.2870546Ada 2012 has introduced mechanisms for exploiting multiprocessor platforms at the application level. These include task affinity control and definition of dispatching domains. However, there are other executable entities defined in the language for which there is no such support to affinity control: event handlers. With event handlers we mean both timing-event and interrupt handlers. This paper discusses the consequences of this lack of functionality and explores implementation issues related with this ability. We propose a working implementation for affinity of timing-event handlers on top of Linux.Sáez Barona, S.; Real Sáez, JV.; Crespo Lorente, A. (2015). Implementation of Timing-Event Affinities in Ada/Linux. Ada Letters. 35(1):80-92. doi:10.1145/2870544.2870546S8092351M. Aldea, A. Burns, M. Gutirrez, and M. González Harbour. Incorporating the deadline floor protocol in Ada. ACM SIGAda Ada Letters -- Proc. of IRTAW 16, XXXIII(2):49--58, 2013.B.B. Brandenburg and J.H. Anderson. Feather-trace: A light-weight event tracing toolkit. In Proc. OSPERT, 2007.A. Burns. A Deadline-Floor Inheritance Protocol for EDF Scheduled Real-Time Systems with Resource Sharing. Technical Report YCS-2012-476, Department of Computer Science, University of York, UK, 2012.A. Burns, M. Gutierrez, M. Aldea, and M. González Harbour. A deadlinefloor inheritance protocol for EDF scheduled embedded real-time systems with resource sharing. IEEE Transactions on Computers, (Online PrePrints), 2014.H. Franke, R. Russell, and M. Kirkwood. Fuss, futexes and furwocks: Fast userlevel locking in linux. In AUUG Conference Proceedings, pages 85--97. AUUG, Inc., 2002.C. Li, C. Ding, and K. Shen. Quantifying the cost of context switch. In Proceedings of the 2007 Workshop on Experimental Computer Science, ExpCS '07. ACM, 2007.R. Spliet, M. Vanga, B.B. Brandenburg, and S. Dziadek. Fast on average, predictable in the worst case: Exploring real-time futexes in litmus. In Proc. IEEE Real-Time Systems Symposium, pages 96--105. IEEE, 2014

Adding multiprocessor and mode change support to the Ada real-time framework

© ACM, 2013. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in Ada Letters, April 2013, Volume XXXIII, Number 1. http://doi.acm.org/10.1145/2492312.2492324[EN] Based on a previous proposal of an Ada 2005 framework of real-time utilities, this paper deals with the extension of that framework to include support for multiprocessor platforms and multiple operating modes and mode changes. The design of the proposed framework is also intended to be amenable to automatic code generation.This work is partly funded by the Vicerrectorado de Investigacion of Universitat Politècnica de València under grant PAID-06-10-2397 and the Europan Commission’s OVERSEE project (FP7-ICT-2009-4, Project ID 248333).Sáez Barona, S.; Real Sáez, JV.; Crespo Lorente, A. (2013). Adding multiprocessor and mode change support to the Ada real-time framework. Ada Letters. 33(1):116-127. https://doi.org/10.1145/2492312.2492324S11612733

Combined Scheduling of Time-Triggered Plans and Priority Scheduled Task Sets

© Owner/Author (2016). This is the author's version of the work. It is posted here for your personal use. Not for redistribution. The definitive Version of Record was published in ACM SIGAda Ada Letters, 36(1), 68-76, http://dx.doi.org/10.1145/10.1145/2971571.2971580.[EN] Preemptive, priority-based scheduling on the one hand, and time-triggered scheduling on the other, are the two major techniques in use for development of real-time and embedded software. Both have their advantages and drawbacks with respect to the other, and are commonly adopted in mutual exclusion. In a previous paper, we proposed a software architecture that enables the combined and controlled execution of time-triggered plans and priority-scheduled tasks. The goal was to take advantage of the best of both approaches by providing deterministic, jitter-controlled execution of time-triggered tasks (e.g., control tasks), coexisting with a set of priority-scheduled tasks, with less demanding jitter requirements. In this paper, we briefly describe the approach, in which the time-triggered plan is executed at the highest priority level, controlled by scheduling decisions taken only at particular points in time, signalled by recurrent timing events. The rest of priority levels are used by a set of concurrent tasks scheduled by static or dynamic priorities. We also discuss several open issues such as schedulability analysis, use of the approach in multiprocessor architectures, usability in mixed-criticality systems and needed changes to make this approach Ravenscar compliant.This work has been partly supported by the Spanish Government’s project M2C2 (TIN2014-56158-C4-1-P-AR) and the European Commission’s project EMC2 (ARTEMIS-JU Call 2013 AIPP-5, Contract 621429).Real Sáez, JV.; Sáez Barona, S.; Crespo Lorente, A. (2016). Combined Scheduling of Time-Triggered Plans and Priority Scheduled Task Sets. Ada Letters. 36(1):68-76. https://doi.org/10.1145/2971571.2971580S6876361T. P. Baker and A. Shaw. The cyclic executive model and Ada. In Proceedings IEEE Real Time Systems Symposium 1988, Huntsville, Alabama, pages 120--129, 1988.P. Balbastre, I. Ripoll, J. Vidal, and A. Crespo. A Task Model to Reduce Control Delays. Real-Time Systems, 27(3):215--236, September 2004.A. Burns and R. Davis. Mixed Criticality Systems - A Review. Technical report, Depatment of Computer Science, University of York, 2013.A. Cervin. Integrated Control and Real-Time Scheduling. PhD thesis, Lund Institute of Technology, April 2003.R. Dobrin. Combining Offline Schedule Construction and Fixed Priority Scheduling in Real-Time Computer Systems. PhD thesis, Mälardalen University, 2005.S. Hong, X. Hu, and M. Lemmon. Reducing Delay Jitter of Real-Time Control Tasks through Adaptive Deadline Adjustments. In IEEE Computer Society, editor, 22nd Euromicro Conference on Real-Time Systems -- ECRTS, pages 229--238, 2010.J. W. S. Liu. Real-Time Systems. Prentice-Hall Inc., 2000.J. Palencia and M. González-Harbour. Schedulability Analysis for Tasks with Static and Dynamic Offsets. In 9th IEEE Real-Time Systems Symposium, 1998.M. J. Pont. The Engineering of Reliable Embedded Systems: LPC1769 edition. Number ISBN: 978-0-9930355-0-0. SafeTTy Systems Limited, 2014.J. Real and A. Crespo. Incorporating Operating Modes to an Ada Real-Time Framework. Ada Letters, 30(1):73--85, April 2010.J. Real, S. Sáez, and A. Crespo. Combining time-triggered plans with priority scheduled task sets. In M. Bertogna and L. M. Pinho, editors, Reliable Software Technologies -- Ada-Europe 2016, volume 9695 of Lecture Notes in Computer Science. Springer, June 2016.S. Sáez, J. Real, and A. Crespo. An integrated framework for multiprocessor, multimoded real-time applications. In M. Brorsson and L. Pinho, editors, Reliable Software Technologies -- Ada-Europe 2012, volume 7308, pages 18--34. Springer-Verlag, June 2012.S. Sáez, J. Real, and A. Crespo. Implementation of Timing-Event Anities in Ada/Linux. Ada Letters, 35(1), April 2015.A. J. Wellings and A. Burns. A Framework for Real-Time Utilities for Ada 2005. Ada Letters, XXVII(2), August 2007